Cadence VCC 2.0 Delivers New Modeling Capabilities for Platform-based Design, Optimizing Time-to-market and SoC Design Chain Interaction
SAN JOSE, Calif.----Sept. 25, 2000--
Cadence Design Systems (NYSE:CDN), the world's leading supplier
of electronic design products and services, today announced a variety
of new capabilities for system-level designers with the latest release
of its market-leading Virtual Component Co-Design (VCC) environment
for platform-based design.
VCC 2.0 delivers new modeling features especially geared for
performing rapid evaluations of implementation alternatives for new
and derivative products early in the design cycle, thus enabling
better and more efficient coordination between SoC providers and
system integrators. In addition, the VCC environment has also been
more tightly integrated with co-verification and implementation flows.
VCC 2.0 introduces a new level of interaction into the
relationship between SoC providers and system integrators by elevating
the decision-making about functional and architectural alternatives to
the system level. For SoC developers, VCC 2.0 provides an open
modeling infrastructure to model specific highlights of their virtual
components (IP) through a set of ``architecture services''. It provides
a comprehensive library of more than 40 such services from
asynchronous delays to time-sliced buses and also allows the modeling
of custom architectural services. System integrators use the VCC
environment to more efficiently articulate their product needs and to
assess the integration aspects of components at the system level at
the earliest point in the design cycle.
``The promise of true SoC design is dependent on the ability to
quickly and efficiently integrate multiple IP blocks as a complete
system,'' Frank Schirrmeister, director of product management for
co-design technology at Cadence®. ``The earlier and the more
accurately system architects can evaluate their alternatives, the
better chance of a working system design being completed faster. With
this release of our pioneering system design tool we are addressing
these critical up-front evaluation issues, as well as the often
forgotten about, yet as critical, challenges of linking the system
design to actual implementation.''
The open VCC 2.0 architectural modeling infrastructure --
providing the industry's most robust platform for IP specification,
evaluation, selection and, integration -- improves the accuracy of
evaluating the impact of communication between functions and their
performance. Specifically, the performance impact of memories and
their hierarchy, caches, queues, timers, direct memory accesses (DMA),
memory management units (MMU), real-time operating systems (RTOS), and
bus-protocols can be explored very early in the design cycle prior to
committing to the implementation of a new or derivative designs.
``As an original development partner during the development of VCC,
our focus has been the modeling of the IP in our SoC platforms,'' said
Jean-Marc Chateau, director of design, consumer and micro groups, ST
Microelectronics. ``The memory and cache modeling features in VCC 2.0
will allow us and our customers to explore the impact of different
memory hierarchies on overall system performance before we commit to
implementation of our SoC platforms. VCC 2.0 will significantly
optimize the interaction with our SoC customers to negotiate the
system specification.''
``By using VCC's performance modeling techniques, we are creating
libraries of reusable blocks that have known high-fidelity performance
estimates,'' said Marinus van Lier, design technology group, Philips
Semiconductors B.V. ``Armed with this advanced understanding of a
blocks performance characteristics, our designers can assess
partitioning decisions and make choices of IP far earlier in the
design process than ever before at the system level. By modeling
overall system performance, they can proceed with confidence that
their decisions are positively affecting achievement of performance
goals. Product developments will have fewer design iterations and
products will reach the market faster than ever. Our first results are
so encouraging that we are now deploying VCC methodology on one of our
highest profile projects, the Nexperia Digital Video Platform, one of
our Silicon System Platforms, whose system chips will power the next
generation of digital convergence appliances for the home.''
Tight Links to Co-Verification and Complete Design Flow
Cadence is the first provider of a complete flow from system-level
design through the validation of system architecture implementation,
including interfaces between hardware and software components in the
SoC integration. After design refinement the VCC environment assembles
and generates C code for the software portion of the design and HDL
for the hardware portion and then exports the data to the appropriate
tools. The VCC environment also allows the design and its test-bench
to be exported to a lower level of abstraction for co-verification of
its hardware and software components.
In VCC 2.0, tighter links to industry-leading implementation tools
have been added. Now, VCC 2.0 also creates the top-level shell of
custom hardware blocks, which share several functions. Joined bus
interfaces and communication between the blocks is automatically
synthesized to speed up the design process from system level to
implementation. This process identifies all blocks in a custom
hardware communication to external modules and synthesizes the
necessary buffer structures and bus interfaces accordingly.
``We have successfully modeled functions and components at the
highest possible level of abstraction for automotive and wireless
applications for Motorola micro-controllers,'' said Andreas Kanstein,
senior CAD engineer Motorola SPS. ``The Cadence VCC environment's
separation of function and architecture significantly speeds up the
design process and helps to efficiently make design tradeoffs. Cadence
VCC, with its link to implementation, will further improve efficiency
by simplifying the interface between the system designer and the
semiconductor provider.''
Optimizing the SoC Design Chain Interaction
The VCC environment provides software and hardware virtual
component vendors with a method for promoting and distributing
critical information to ensure successful design and integration of IP
blocks for platform-based designs. It also allows system companies and
silicon vendors to efficiently interact using system-level virtual
prototypes, optimize product specifications, shorten development
cycles, and capitalize on the increased capabilities offered by
multi-million gate integrated circuits.
``A true co-design environment must support essential architectural
elements such as the central processing unit, real-time operating
system, buses, memory and dedicated hardware and software,'' said Dr.
Maximilian Fuchs, manager of the software development process, BMW AG.
``To improve time-to-market, each component must be modeled at a higher
level of abstraction earlier in the design process.'' As one of the
participants in the Felix initiative, we have been able use the
Cadence VCC environment to do virtual system integration of our
designs by proving functionality of various system configurations
before implementation. The Cadence VCC environment will become an
instrumental part in our system design process and will play the role
of the virtual integration platform.``
Cadence Augments Services for Co-Development
Cadence offers customers a comprehensive range of services that
can help accelerate adoption of a HW/SW co-development methodology and
integration of the VCC product into their existing development
environments. The VCC services package includes tool efficiency
training, Quickstart programs, and methodology consulting to recommend
a design process that best leverages the VCC environment.
Pricing and Availability
After an extensive beta testing period, VCC 2.0 is available today
on Unix-based workstations from Sun Microsystems and Windows NT
operating platforms. Special packages for system integrators (VCC
Evaluator) and SoC providers (VCC Architect) are available. Pricing
starts at $52,800 for a one-year license. For information regarding
international pricing, please contact the local or regional Cadence
sales office.
About Cadence
Cadence is the largest supplier of electronic design automation
products, methodology services, and design services used to accelerate
and manage the design of semiconductors, computer systems, networking
and telecommunications equipment, consumer electronics, and a variety
of other electronics-based products. With approximately 5,100
employees and 1999 annual revenue of $1.1 billion, Cadence has sales
offices, design centers, and research facilities located around the
world. The company is headquartered in San Jose, Calif., and traded on
the New York Stock Exchange under the symbol CDN. For more
information, visit http://www.cadence.com.
Cadence and the Cadence logo are registered trademarks. All other
trademarks are the properties of their owners.
Contact:
Cadence Design Systems, Inc.
Valerie J. Smith, 408/428-5795
vsmith@cadence.com
or
Wired Island, Ltd.
Mike Sottak for Cadence, 649/941-4218
mike@wiredisland.tc
|
